Semiconductor memory

ABSTRACT

A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 6,643,167. The reissue applications that have beenfiled include parent reissue application Ser. No. 11/265,744 filed onNov. 3, 2005, and reissue application Ser. No. 12/846,450 filed Jul. 29,2010, and reissue application Ser. No. 13/863,011 filed Apr. 15, 2013,and the present reissue application which is a continuation reissue ofthe '011 reissue application.

This application is a Continuation of U.S. application Ser. No.13/863,011, filed on Apr. 15, 2013, now U.S. Pat. No. RE46,272, issuedon Jan. 10, 2017, which is a Continuation of U.S. application Ser. No.12/846,450, filed on Jul. 29, 2010, now U.S. Pat. No. RE44,242, issuedon May 28, 2013, which is a Continuation of U.S. application Ser. No.11/265,744, filed on Nov. 3, 2005, now U.S. Pat. No. RE41,638, issued onSep. 7, 2010, which is a Reissue of U.S. application Ser. No.10/350,221, filed on Jan. 24, 2003, now U.S. Pat. No. 6,643,167, issuedon Nov. 4, 2003, which is a Continuation of U.S. application Ser. No.09/900,917, filed on Jul. 10, 2001, now U.S. Pat. No. 6,529,401, issuedon Mar. 4, 2003.

This application is also a Reissue of U.S. application Ser. No.10/350,221, filed on Jan. 24, 2003, now U.S. Pat. No. 6,643,167, issuedon Nov. 4, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory and, inparticular, to a memory cell structure having improvements in resistanceto soft error of a MOS static RAM.

2. Description of the Background Art

As the miniaturization of memory cells proceeds, the following softerror problem becomes noticeable. Specifically, the data stored in astorage node is inverted due to electrons generated from alpha raysreleased from a package and neutron beams from outer space.Particularly, as power supply voltage is lowered, malfunction becomesmore significant. Attempts to reduce soft error are being pursued.

FIG. 37 is a circuit diagram illustrating a structure equivalent to aSRAM memory cell disclosed in, for example, Japanese Patent No. 2589949.As shown in FIG. 37, a memory cell 100 is made up of PMOS transistorsPT1 and PT2, and NMOS transistors NT5 to NT8, NT11, NT12, NT21 and NT22.

The sources of the PMOS transistors PT1 and PT2 are both connected to apower supply voltage V_(cc). The drain of the PMOS transistor PT1 isconnected through a node 101 to the gate of the PMOS transistor PT2 andto the gates of the NMOS transistors NT21 and NT22. The drain of thePMOS transistor PT2 is connected through a node 111 to the gate of thePMOS transistor PT1 and to the gates of the NMOS transistors NT11 andNT12.

The sources of the NMOS transistors NT11 and NT12 are both grounded. Thedrain of the NMOS transistor NT11 is connected through the node 101 tothe drain of the PMOS transistor PT1. The drain of the NMOS transistorNT12 is connected through the nodes 101 and 102 to the drain of the PMOStransistor PT1.

The sources of the NMOS transistors NT21 and NT22 are both grounded. Thedrain of the NMOS transistor NT21 is connected through the node 111 tothe drain of the PMOS transistor PT2. The drain of the NMOS transistorNT22 is connected through the nodes 111 and 112 to the drain of the PMOStransistor PT2.

The NMOS transistor NT5 is interposed between a bit line BL50 and thenode 101, and its gate is connected to a word line WL50. The NMOStransistor NT6 is interposed between a bit line BL60 and the node 101,and its gate is connected to a word line WL60. The NMOS transistor NT7is interposed between a bit line BL51 and the node 111, and its gate isconnected to the word line WL50. The NMOS transistor NT8 is interposedbetween a bit line BL61 and the node 111, and its gate is connected tothe word line WL60.

In such a configuration, the word line WL50 or WL60 is brought into theactive state and the NMOS transistors NT5 and NT6, or the NMOStransistors NT6 and NT8 are brought into the on state, thereby toprovide access to the nodes 101 and 111, each being a storage node. Thisenables to obtain the data from the paired bit lines BL50 and BL51 orthe paired bit lines BL60 and BL61.

In this configuration, a NMOS driver transistor that is usually made upof a single NMOS transistor is divided into two NMOS transistors (whichis divided into the NMOS transistors NT11 and NT12, and NT21 and NT22).

In order to divide the storage node serving as the drain of the PMOStransistor PT1 (PT2) into the node 101 (111) and the node 102 (112), theNMOS transistor NT11 (NT21) and the NMOS transistor NT12 (NT22) areoppositely disposed so as to interpose therebetween an N well regionwhere the PMOS transistor PT1 is to be formed.

Therefore, the N well region prevents that a depletion region on theopposite side of the N well region is adversely affected by electrons orholes generated from energy particles colliding with one side of the Nwell region. This enables to lower incidence of soft error.

However, even with the foregoing SRAM memory cell, a reduction in softerror is insufficient. Further, there is the problem that the circuitconfiguration is complicated by using two driver transistors, althoughit can be generally configured by using one.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, a semiconductor memoryhaving a memory cell containing first and second inverters subjected tocross connection, a first conductivity type being defined by first kind,and a second conductivity type being defined by second kind, ischaracterized in that: the first inverter consists of a first fieldeffect transistor of the first kind and a first field effect transistorof the second kind; that the second inverter consists of a second fieldeffect transistor of the first kind and a second field effect transistorof the second kind; and that the first and second field effecttransistors of the first kind are disposed in separate first and secondwell regions of the second kind, respectively.

According to a second aspect of the invention, the semiconductor memoryof the first aspect is characterized in that: an output part of thefirst inverter includes a connecting part between one electrode of thefirst field effect transistor of the first kind and one electrode of thefirst field effect transistor of the second kind, an input part thereofincludes a connecting part between a control electrode of the firstfield effect transistor of the first kind and a control electrode of thefirst field effect transistor of the second kind; an output part of thesecond inverter includes a connecting part between one electrode of thesecond field effect transistor of the first kind and one electrode ofthe second field effect transistor of the second kind, and an input partthereof includes a connecting part between a control electrode of thesecond field effect transistor of the first kind and a control electrodeof the second field effect transistor of the second kind; that thememory cell further includes: (i) a third field effect transistor of thefirst kind, one electrode of which is connected to a first storageterminal electrically connected to the output part of the first inverterand the input part of the second inverter, and the other electrode ofwhich is connected to a first bit line, and a control electrode of whichis connected to a word line; and (ii) a fourth field effect transistorof the first kind, one electrode of which is connected to a secondstorage terminal electrically connected to the output part of the secondinverter and the input part of the first inverter, and the otherelectrode of which is connected to a second bit line, and a controlelectrode of which is connected to a word line; and that the third andfourth field effect transistors of the first kind are disposed in secondand first well regions of the second kind, respectively.

According to a third aspect of the invention, the semiconductor memoryof the second aspect is characterized in that the respective oneelectrodes in the first to fourth field effect transistors of the firstkind are disposed separately.

According to a fourth aspect of the invention, the semiconductor memoryof the second aspect is characterized in that: the first and third fieldeffect transistors of the first kind and the first field effecttransistor of the second kind are arranged in an approximately straightline along the direction of formation of the word line; and that thesecond and fourth field effect transistors of the first kind and thesecond field effect transistor of the second kind are arranged in anapproximately straight line along the direction of formation of the wordline.

According to a fifth aspect of the invention, the semiconductor memoryof the first aspect is characterized in that the first and second fieldeffect transistors of the first kind are arranged so as to be pointsymmetry with respect to the central point of the memory cell.

According to a sixth aspect of the invention, the semiconductor memoryof the second aspect is characterized in that the third and fourth fieldeffect transistors of the first kind are arranged so as to be pointsymmetry with respect to the central point of the memory cell.

According to a seventh aspect of the invention, the semiconductor memoryof the second aspect is characterized in that the width of the controlelectrode of the first and second field effect transistors of the firstkind is set so as to be larger than the width of the control electrodeof the third and fourth field effect transistors of the first kind.

According to an eighth aspect of the invention, the semiconductor memoryof one of the foregoing aspects is characterized in that the memory cellfurther includes (i) a first resistance component interposed between theinput part of the first inverter and the second storage terminal, and(ii) a second resistance component interposed between the input part ofthe second inverter and the first storage terminal.

According to a ninth aspect of the invention, the semiconductor memoryof the eighth aspect is characterized in that the first and secondresistance components include a high resistance metal wiring formed froma metal material having a higher resistivity than CoSi.

According to a tenth aspect of the invention, the semiconductor memoryof the eighth aspect is characterized in that the first and secondresistance components include a high resistance polysilicon wiringformed from polysilicon having a higher resistivity than CoSi.

According to an eleventh aspect of the invention, the semiconductormemory of the second aspect is characterized in that the controlelectrodes of the third and fourth field effect transistors of the firstkind and the word line are formed by using a single polysilicon.

According to a twelfth aspect of the invention, the semiconductor memoryof the second aspect is characterized in that: the word line includesseparate first and second word lines; that the control electrode of thethird field effect transistor of the first kind is connected to thefirst word line; and that the control electrode of the fourth fieldeffect transistor of the first kind is connected to the second wordline.

According to a thirteenth aspect of the invention, the semiconductormemory of the twelfth aspect is characterized in that: the first bitline includes first and second partial bit lines forming a pair of bitlines; that the second bit line includes third and fourth partial bitlines forming a pair of bit lines; that the third field effecttransistor of the first kind includes fifth and sixth field effecttransistors of the first kind, the fifth field effect transistor of thefirst kind being interposed between the first partial bit line and thesecond storage terminal, the sixth field effect transistor of the firstkind being interposed between the second partial bit line and the firststorage terminal; and that the fourth field effect transistor of thefirst kind includes seventh and eighth field effect transistors of thefirst kind, the seventh field effect transistor of the first kind beinginterposed between the third partial bit line and the first storageterminal, the eighth field effect transistor of the first kind beinginterposed between the fourth partial bit line and the second storageterminal.

According to a fourteenth aspect of the invention, the semiconductormemory of the thirteenth aspect is characterized in that the width ofthe control electrode of the first and second field effect transistorsof the first kind is set so as to be larger than the width of thecontrol electrode of the fifth to eighth field effect transistors of thefirst kind.

According to a fifteenth aspect of the invention, the semiconductormemory of the second, twelfth or thirteenth aspect is characterized inthat a region for forming the control electrode of the first and secondfield effect transistors of the first kind is disposed so as to form aportion of the second and first storage terminals, respectively.

According to a sixteenth aspect of the invention, the semiconductormemory of one of the foregoing aspects is characterized in that: thefirst and second field effect transistors of the second kind aredisposed in a well region of the first kind; and that the well region ofthe first kind is disposed between the first and second well regions ofthe second kind.

In the semiconductor memory of the first aspect, the first and secondfield effect transistors of the first kind are disposed in the separatefirst and second well region of the second kind, respectively.Therefore, if carriers generated from alpha rays, etc. are collectedinto one or the other electrode region of one of the first and secondfield effect transistor of the first kind, such carriers are cancelledby being released from one or the other electrode region of the other ofthe first and second field effect transistor of the first kind on whichno influence of the carriers is exerted. This enables to increaseresistance to soft error.

In addition, since the first and second inverters each consists of acombination of a field effect transistor of the first kind and that ofthe second kind, a complementary type can be realized by at leastsufficient circuit configuration.

In the semiconductor memory of the second aspect, the third and fourthfield effect transistors of the first kind are disposed in the secondand first well regions of the second kind, respectively. Thereby, thememory cell selecting operation by means of the word line, and thewrite/read operation to the memory cell via the first and second bitlines, are executable while improving resistance to soft error.

In the semiconductor memory of the third aspect, resistance to softerror can be increased by separately forming one electrode to beconnected to the first or second storage terminal in the first to fourthfield effect transistors of the first kind.

In the semiconductor memory of the fourth aspect, the degree ofintegration can be increased by virtue of the layout of the first tofourth field effect transistors of the first kind and the first andsecond field effect transistors of the second kind.

In the semiconductor memory of the fifth aspect, by disposing the firstand second MOS transistors so as to be point symmetry with respect tothe central portion of the memory cell, arrangement between adjacentmemory cells can be facilitated to increase the degree of integration.

In the semiconductor memory of the sixth aspect, by disposing the thirdand fourth MOS transistors so as to be point symmetry with respect tothe central portion of the memory cell, arrangement between adjacentmemory cells can be facilitated to increase the degree of integration.

In the semiconductor memory of the seventh aspect, the stability of thememory cell can be increased by setting such that the control electrodewidth of the first and second field effect transistors of the first kindis larger than that of the third and fourth field effect transistors ofthe first kind.

In the semiconductor memory of the eighth aspect, by signal propagationdelay due to the first and second resistance components, the responsecharacteristic for inverting the data held in the first and secondstorage terminals of the memory cell can be elongated, thereby softerror is hard to occur.

The semiconductor memory of the ninth aspect realizes the first andsecond resistance components by using the high resistance polysiliconwiring.

The semiconductor memory of the tenth aspect realizes the first andsecond resistance components by using the high resistance polysiliconwiring.

In the semiconductor memory of the eleventh aspect, by using a singlepolysilicon common to the control electrodes and word lines of the thirdand fourth MOS transistors, the number of layers to be formed can bereduced, thereby allowing for a reduction in the cost of thesemiconductor memory.

In the semiconductor memory of the twelfth aspect, by the presence oftwo memory cell selecting means composed of the first and second wordlines, the memory cell can be used for FIFO memory.

The semiconductor memory of the thirteenth aspect realizes a two-portmemory cell composed of the first to fourth partial bit lines and thefirst and second word lines.

In the semiconductor memory of the fourteenth aspect, the stability ofthe memory cell can be increased by setting such that the controlelectrode width of the first and second field effect transistors of thefirst kind is larger than that of the fifth to eighth field effecttransistors of the first kind.

In the semiconductor memory of the fifteenth aspect, with thearrangement such that the region for forming the control electrode ofthe first and second field effect transistors of the first kind forms aportion of the second and first storage terminals, respectively, theregion for forming memory cell can be narrowed to increase the degree ofintegration.

In the semiconductor memory of the sixteenth aspect, by the well regionof the first kind disposed between the first and second well regions ofthe second kind, it is avoided that carriers generated in the first orsecond well region of the second kind exert influence on the other wellregion of the second kind.

It is an object of the present invention to overcome the foregoingproblem by providing a semiconductor memory having a memory cellstructure capable of reducing soft error without complicating a circuitconfiguration.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a firstpreferred embodiment of the invention;

FIG. 2 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 1;

FIG. 3 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 1;

FIG. 4 is a circuit diagram illustrating an equivalent circuit of thememory cell in the first preferred embodiment;

FIG. 5 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a secondpreferred embodiment of the invention;

FIG. 6 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 5;

FIG. 7 is an explanatory diagram viewed from above the layoutconfiguration beneath the first aluminum wiring layer between adjacentmemory cells;

FIG. 8 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a thirdpreferred embodiment of the invention;

FIG. 9 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 8;

FIG. 10 is a circuit diagram illustrating an equivalent circuit of thememory cell in the third preferred embodiment;

FIG. 11 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a fourthpreferred embodiment of the invention;

FIG. 12 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 11;

FIG. 13 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a fifthpreferred embodiment of the invention;

FIG. 14 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 13;

FIG. 15 is a circuit diagram illustrating an equivalent circuit of thememory cell in the fifth preferred embodiment;

FIG. 16 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a sixthpreferred embodiment of the invention;

FIG. 17 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 16;

FIG. 18 is an explanatory diagram viewed from above mainly the layoutconfiguration above a second aluminum wiring layer in FIG. 16;

FIG. 19 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a seventhpreferred embodiment of the invention;

FIG. 20 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 19;

FIG. 21 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 19;

FIG. 22 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to an eighthpreferred embodiment of the invention;

FIG. 23 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 22;

FIG. 24 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 22;

FIG. 25 is a circuit diagram illustrating an equivalent circuit of thememory cell in the eighth preferred embodiment;

FIG. 26 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a ninthpreferred embodiment of the invention;

FIG. 27 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 26;

FIG. 28 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 26;

FIG. 29 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a tenthpreferred embodiment of the invention;

FIG. 30 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 29;

FIG. 31 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 29;

FIG. 32 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to aneleventh preferred embodiment of the invention;

FIG. 33 is an explanatory diagram viewed from above mainly the layoutconfiguration beneath a first aluminum wiring layer in FIG. 32;

FIG. 34 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 32;

FIG. 35 is an explanatory diagram viewed from above the layoutconfiguration in all layers of a SRAM memory cell according to a twelfthpreferred embodiment of the invention;

FIG. 36 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 35; and

FIG. 37 is a circuit diagram illustrating a conventional SRAM memorycell.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

FIGS. 1 to 4 are diagrams illustrating a memory cell structure of a SRAMaccording to a first preferred embodiment of the invention. FIG. 1 is anexplanatory diagram viewed from above the layout configuration in alllayers. FIG. 2 is an explanatory diagram viewed from above mainly thelayout configuration beneath a first aluminum wiring layer in FIG. 1.FIG. 3 is an explanatory diagram viewed from above mainly the layoutconfiguration over a second aluminum wiring layer in FIG. 1. Somereference numerals used in FIG. 2 or 3 are omitted in FIG. 1.

FIG. 4 is a circuit diagram illustrating an equivalent circuit of theSRAM memory cell of the layout configuration shown in FIGS. 1 to 3. Asseen from FIG. 4, the SRAM memory cell of the first preferred embodimentis made up of NMOS transistors N1 to N4 and PMOS transistors P1 and P2.

The PMOS transistors P1 and P2, each being a driver transistor, aredisposed within an N well region NW. The NMOS transistor N1 that is adriver transistor and the NMOS transistor N4 that is an accesstransistor are disposed within a P well region PW0. The NMOS transistorN2 that is a driver transistor and the NMOS transistor N3 that is anaccess transistor are disposed within a P well region PW1. The P wellregions PW0 and PW1 are oppositely disposed with the N well region NWinterposed therebetween.

A first CMOS inverter I1 is made up of the NMOS transistor N1 and PMOStransistor P1. That is, the gates of the PMOS transistor P1 and NMOStransistor N1 are both connected to a storage terminal Nb, and theirdrains are both connected to a storage terminal Na. The source of thePMOS transistor P1 is connected to a power supply voltage V_(dd), andthe source of the NMOS transistor N1 is grounded.

A second CMOS inverter I2 is made up of the NMOS transistor N2 and PMOStransistor P2. That is, the gates of the PMOS transistor P2 and NMOStransistor N2 are both connected to the storage terminal Na, and theirdrains are both connected to the storage terminal Nb. The source of thePMOS transistor P2 is connected to the power supply voltage V_(dd), andthe source of the NMOS transistor N2 is grounded.

Thus, an output part of the inverter I1 and an input part of theinverter I2 are electrically connected to the storage terminal Na, andan input part of the inverter I1 and an output part of the inverter I2are electrically connected to the storage terminal Nb, so that the CMOSinverters I1 and I2 are subjected to cross section. Thereby, the storageterminals Na and Nb can store information of mutually inverted logicallevel.

The NMOS transistor N3 is interposed between a bit line BLA and thestorage terminal Na, and its gate is connected to a word line WL. TheNMOS transistor N4 is interposed between a bit line BLB and the storageterminal Nb, and its gate is connected to the word line WL.

In such a configuration, the word line WL is brought into the activestate and the NMOS transistors NT3 and NT4 are brought into the onstate, thereby to provide access (i.e., read or write) to the storageterminals Na and Nb. This enables to obtain the data from the bit lineBLA or BLB.

Referring to FIGS. 1 to 3, description will proceed to the memory cellstructure of the first preferred embodiment.

In the N well region NW, the PMOS transistor P1 is made up of P⁺diffusion regions FL110, FL111, and a polysilicon wiring PL1, and thePMOS transistor P2 is made up of P⁺ diffusion regions FL120, FL121, anda polysilicon wiring PL2.

In the P well region PW0, the NMOS transistor N1 is made up of N⁺diffusion regions FL210, FL211, and the polysilicon wiring PL1, and theNMOS transistor N4 is made up of N⁺ diffusion regions FL240, FL241, anda polysilicon wiring PL4. The polysilicon wiring PL1 extends from the Nwell region NW to the P well region PW0, so as to be used as a gatecommon to the NMOS transistor N1 and PMOS transistor P1.

In the P well region PW1, the NMOS transistor N2 is made up of N⁺diffusion regions FL220, FL221, and the polysilicon wiring PL2, and theNMOS transistor N3 is made up of N⁺ diffusion regions FL230, FL231, anda polysilicon wiring PL3. The polysilicon wiring PL2 extends from the Nwell region NW to the P well region PW1, so as to be used as a gatecommon to the NMOS transistor N2 and PMOS transistor P2.

The foregoing diffusion regions FL110, FL111, FL120, FL121, FL210,FL211, FL220, FL221, FL230, FL231, FL240 and FL241 are obtainable byimplanting and diffusing impurity.

A ground wiring LG1 (first layer aluminum wiring) over the diffusionregion FL210 is electrically connected through a diffusion contact hole1C to the diffusion region FL210. An aluminum wiring AL11, which is afirst layer aluminum wiring extending over the diffusion region FL211,FL111 and FL231, is electrically connected through a diffusion contacthole 1C to the diffusion regions FL211, FL111 and FL231, respectively.The aluminum wiring AL11 is also disposed over part of the polysiliconwiring PL2, and is electrically connected through a gate contact hole GCto the polysilicon wiring PL2. The aluminum wiring AL11 can beelectrically connected with low impedance, and it corresponds to thestorage terminal Na.

The diffusion contact hole 1C means a contact hole between a diffusionregion and a first layer (aluminum) wiring. The gate contact hole GCmeans a contact hole between a polysilicon wiring and a first layerwiring.

The polysilicon wiring PL4 is electrically connected through a gatecontact hole GC to the word line WL1 (first layer aluminum wiring). Abit line BLB1 (first layer aluminum wiring) over the diffusion regionFL241 is electrically connected through a diffusion contact hole 1C tothe diffusion region FL241.

An aluminum wiring AL12, which is a first layer aluminum wiringextending over the diffusion regions FL240, FL120 and FL220, iselectrically connected through a diffusion contact hole 1C to thediffusion regions FL240, FL120 and FL220, respectively. The aluminumwiring AL12 is also disposed over part of the polysilicon wiring PL1,and is electrically connected through a gate contact hole GC to thepolysilicon wiring PL1. The aluminum wiring AL12 can be electricallyconnected with low impedance, and it corresponds to the storage terminalNb.

A power supply wiring LV1 (first layer aluminum wiring) over thediffusion region FL110 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL110. The power supply wiringLV1 over the diffusion region FL121 is electrically connected through adiffusion contact hole 1C to the diffusion region FL121.

A bit line BLA1 (first layer aluminum wiring) over the diffusion regionFL230 is electrically connected through a diffusion contact hole 1C tothe diffusion region FL230. A word line WL1 over the polysilicon wiringPL3 is electrically connected through a gate contact hole GC to thepolyslicon wiring PL3. A ground wiring LG1 over the diffusion regionFL221 is electrically connected through a diffusion contact hole 1C tothe diffusion region FL221.

A ground wiring LG1 is electrically connected through a via hole 1T to aground wiring LG2 (second layer aluminum wiring (2AL)), and the groundwiring LG2 is electrically connected through a via hole 2T to a groundwiring LG3 (third layer aluminum wiring (3AL)).

A word line WL1 is electrically connected through a via hole 1T to aword line WL2 (second layer aluminum wiring), and the word line WL2 iselectrically connected through a via hole 2T to a word line WL3 (thirdlayer aluminum wiring). The word line WL shown in FIG. 4 is made up ofthese word lines WL1 to WL3.

The via hole 1T means a via hole to make connection between a firstlayer wiring and a second layer (aluminum) wiring. The via hole 2T meansa via hole to make connection between a second layer wiring and a thirdlayer (aluminum) wiring.

The word line WL3 and ground wiring LG3 are disposed parallel with eachother, across the P well regions PW0, PW1, and the N well region NW. Twoground wirings LG3 are disposed with the word line WL3 interposedtherebetween.

A bit line BLA2 (second layer aluminum wiring) is electrically connectedthrough a via hole 1T to a bit line BLA1 (not shown in FIG. 3). A bitline BLB2 (second layer aluminum wiring) is electrically connectedthrough a via hole 1T to a bit line BLB1 (not shown in FIG. 3). A powersupply wiring LV2 (second layer aluminum wiring) is electricallyconnected through a via hole 1T to a power supply wiring LV1 (not shownin FIG. 3). The bit lines BLA and BLB shown in FIG. 4 are made up of thebit lines BLA1 and BLA2, and the bit lines BLB1 and BLB2, respectively.

The bit lines BLA2, BLB2 and the power supply wiring LV2 are disposedover the P well regions PW1, PW0 and the N well region NW, respectively,so as to be parallel to each other in the longitudinal direction viewingthe drawing.

Thus, in the memory cell structure of the SRAM of the first preferredembodiment, with the N well region NW interposed between the P wellregions PW0 and PW1, the NMOS transistors N1 and N4 are disposed in theP well region PW0, and the NMOS transistors N2 and N3 are disposed inthe P well region PW1. Thereby, the N⁺ diffusion region FL211 and the N⁺diffusion region FL220 that are electrically connected to the storageterminals Na and Nb, respectively, can be separately formed in thedifferent P well regions PW0 and PW1.

As a result, there are the following effects. Firstly, when electronsgenerated from alpha rays and neutron beams are collected into the N⁺diffusion region formed in one of the P well regions PW0 and PW1, suchelectrons are released from the N⁺ diffusion region formed in the otherP well region where the influence of the generated electrons can beavoided by the presence of the N well region NW. This cancels out theoccurrence of electrons acting to invert the hold data of the storageterminals Na and Nb, and thus the inversion of data is hard to occur.That is, there is the effect of improving resistance to soft error (Thisis hereinafter referred to as the first effect.).

Secondly, since the P well regions PW0 and PW1 are separately formed ina direction vertical to the direction of formation of the bit lines BLAand BLB, the formation of the two P well regions PW0 and PW1 exerts noinfluence on the wiring length of the bit lines BLA and BLB. Hence,there is no possibility that the formation of the P well regions PW0 andPW1 increases the wiring length of the bit lines, thus maintaining agood access time (This is hereinafter referred to as the secondeffect.).

Thirdly, since the NMOS transistors N1 and N2, and the NMOS transistorsN3 and N4, are respectively arranged so as to be point symmetry withrespect to the central part of the memory cell (the central part of theN well region NW), the degree of integration can be increased when aplurality of the memory cells of the first preferred embodiment aredisposed adjacent each other (This is hereinafter referred to as thethird effect.).

Fourthly, the formation of the polysilicon wirings PL1 to PL4 in thesame direction (the lateral direction viewing the drawing) facilitatesthe control of the gate dimension. Further, because the polysiliconwirings PL1 and PL3 (NMOS transistors N1, N3, and PMOS transistor P1),and the polysilicon wirings PL2 and PL4 (NMOS transistors N2, N4, andPMOS transistor P2) are respectively arranged in a straight line, nowaste region is present and a reduction in the circuit area increasesthe degree of integration (This is hereinafter referred to as the fourtheffect.).

Fifthly, by separately forming a region serving as a drain (i.e., aregion electrically connected to the storage terminal Na or Nb) in theNMOS transistors N1 to N4, resistance to soft error can be maintained ata high level (a fifth effect).

Sixthly, with the arrangement that each of inverters I1 and I2 of a CMOSstructure is made up of a combination of a NMOS transistor and a PMOStransistor, the memory cell can be realized by at least sufficientcircuit configuration as a CMOS structure (a sixth effect).

Second Preferred Embodiment

FIGS. 5 and 6 are diagrams illustrating a memory cell structure of aSRAM according to a second preferred embodiment of the invention. FIG. 5is an explanatory diagram viewed from above the layout configuration inall layers. FIG. 6 is an explanatory diagram viewed from above mainlythe layout configuration beneath a first aluminum wiring layer in FIG.5. An explanatory diagram viewed from above the layout configurationover a second aluminum wiring layer in FIG. 5 is similar to that of FIG.3 in the first preferred embodiment. A circuit diagram illustrating anequivalent circuit of the second preferred embodiment is similar to thatof FIG. 4. Some reference numerals used in FIG. 6 or 3 are omitted inFIG. 5.

As seen from these figures, over a rectangular N⁺ diffusion region for aNMOS transistor N1, a polysilicon wiring PL1 is formed by bending itfrom the central part of the N⁺ diffusion region, so that a relativelywide diffusion region FL212 and a relatively narrow diffusion regionFL213 are formed on the outside and inside of the polysilicon wiringPL1, respectively. The NMOS transistor N1 is made up of the diffusionregions FL212, FL213, and the polysilicon wiring PL1.

Likewise, over a rectangular N⁺ diffusion region for a NMOS transistorN2, a polysilicon wiring PL2 is formed by bending it from the centralpart of the N⁺ diffusion region, so that a relatively wide diffusionregion FL223 and a relatively narrow diffusion region FL222 are formedon the outside and inside of the polysilicon wiring PL2, respectively.The NMOS transistor N2 is made up of the diffusion regions FL222, FL223,and the polysilicon wiring PL2.

A ground wiring LG1 over the diffusion region FL212 is electricallyconnected through two diffusion contact holes 1C to the diffusion regionFL212. An aluminum wiring AL11 over the diffusion region FL213 iselectrically connected through a diffusion contact hole 1C to thediffusion region FL213.

Likewise, a ground wiring LG1 over the diffusion region FL223 iselectrically connected through two diffusion contact holes 1C to thediffusion region FL223. An aluminum wiring AL12 over the diffusionregion FL222 is electrically connected through a diffusion contact hole1C to the diffusion region FL222. Otherwise, the layout configuration issimilar to that of the first preferred embodiment, and the descriptionthereof is thus omitted.

The second preferred embodiment having the foregoing layoutconfiguration produces the following effects in addition to the first,second, fifth and sixth effects of the first preferred embodiment.

It is able to increase the gate width (channel width) of the NMOStransistors N1 and N2 that are driver transistors. As a result, theoperation speed can be increased by quickly removing the carriers of thebit lines BLA and BLB.

Additionally, the ratio of a gate width W to the NMOS transistors N3 andN4, which are the respective access transistors of the NMOS transistorsN1 and N2 that are driver transistors, can be increased to improve thestability of the memory cell.

FIG. 7 is an explanatory diagram viewed from above the layoutconfiguration between adjacent cells. Like FIG. 6, FIG. 7 illustratesmainly the layout configuration beneath a first aluminum wiring layer inFIG. 5.

In FIG. 7, there are shown an N well region NW and a P well region PW0of a memory cell MC1, and an N well region NW and a P well region PW0 ofa memory cell MC2.

The NMOS transistors N1 and N2 are respectively arranged so as to bepoint symmetry with respect to the central part of the memory cell (thecentral part of the N well region NW). This corresponds to the thirdeffect of the first preferred embodiment. Referring to FIG. 7, betweenthe adjacent memory cells MC1 and MC2, the NMOS transistors N1 (N2),each being a driver transistor, can be disposed adjacent each other inline symmetric relation, thereby to increase the gate width W of theNMOS transistors N1 and N2, while increasing the degree of integrationby having the diffusion region FL212, word line WL1, ground wiring LG1,diffusion contact hole 1C and gate contact hole GC share at least theirrespective portions.

Thus, there is little or no increase of area due to the bending of thepolysilicon wirings PL1 and PL2 that become the gates of the NMOStransistors N1 and N2, respectively. It is therefore able to obtain ahigh-density memory cell structure similar to that of the firstpreferred embodiment.

In addition, the degree of integration can be increased by disposing theNMOS transistors N1, N3 and PMOS transistor P1; and the NMOS transistorsN2, N4 and PMOS transistor P2, in an approximately straight line,respectively. This corresponds to the fourth effect of the firstpreferred embodiment.

Third Preferred Embodiment

FIGS. 8 to 10 are diagrams illustrating a memory cell structure of aSRAM according to a third preferred embodiment of the invention. FIG. 8is an explanatory diagram viewed from above the layout configuration inall layers. FIG. 9 is an explanatory diagram viewed from above mainlythe layout configuration beneath a first aluminum wiring layer in FIG.8. An explanatory diagram viewed from above the layout configurationover a second aluminum wiring layer in FIG. 8 is similar to that of FIG.3 in the first preferred embodiment. Some reference numerals used inFIG. 9 or 3 are omitted in FIG. 8.

FIG. 10 is a circuit diagram illustrating an equivalent circuit of theSRAM memory cell having the layout configuration shown in FIGS. 8, 9 and3. Referring to FIG. 10, a resistance R1 is interposed between a storageterminal Nb and the gate of a NMOS transistor N1 and a PMOS transistorP1. A resistance R2 is interposed between a storage terminal Na and thegate of a NMOS transistor N2 and a PMOS transistor P2. Otherwise, theconfiguration is similar to that of the first preferred embodimentdescribed with respect to FIG. 4, and the description thereof is thusomitted.

Referring to FIGS. 8, 9 and 3, description will proceed to the memorycell structure of the third preferred embodiment.

As shown in these figures, a polysilicon wiring PL13 (corresponding tothe polysilicon wiring PL1 of the first preferred embodiment), whichbecomes the gate of the NMOS transistor N1 and PMOS transistor P1, iselectrically connected to a high resistance metal wiring M00 thatbecomes the resistance R1. The high resistance metal wiring M00 iselectrically connected through a via hole 0T to an aluminum wiring AL12that is the storage terminal Nb. The via hole 0T means a via hole tomake connection between the high resistance metal wiring M00 formed inthe same layer as the polysilicon wiring, and a first layer wiring.

Likewise, a polysilicon wiring PL14 (corresponding to the polysiliconwiring PL2 of the first preferred embodiment), which becomes the gate ofthe NMOS transistor N2 and PMOS transistor P2, is electrically connectedto a high resistance metal wiring M01 that becomes the resistance R2.The high resistance metal wiring M01 is electrically connected through avia hole 0T to the aluminum wiring AL11 that is the storage terminal Na.

Examples of material of the high resistance metal wirings M00 and M01are tungsten, etc., having a higher resistivity than CoSi (cobaltsilicon). Otherwise, the configuration is similar to that of the firstpreferred embodiment described with respect to FIGS. 1 to 3, and thedescription thereof is thus omitted.

The third preferred embodiment having the foregoing memory cellstructure produces the following effect in addition to the first tosixth effects of the first preferred embodiment.

In the memory cell of the third preferred embodiment, the responsecharacteristic for inverting the data held in the cell is elongated dueto signal delay propagating the resistances R1 and R2. As a result, evenif the potential of one of the storage terminals Na and Nb is invertedby electrons generated from alpha rays and neutron beams, it returns tothe initial hold state before the data of the other storage terminal isinverted, thereby soft error becomes much rare.

Fourth Preferred Embodiment

FIGS. 11 and 12 are diagrams illustrating a memory cell structure of aSRAM according to a fourth preferred embodiment of the invention. FIG.11 is an explanatory diagram viewed from above the layout configurationin all layers. FIG. 12 is an explanatory diagram viewed from abovemainly the layout configuration beneath a first aluminum wiring layer inFIG. 11. An explanatory diagram viewed from above the layoutconfiguration over a second aluminum wiring layer in FIG. 11 is similarto that of FIG. 3 in the first preferred embodiment. Some referencenumerals used in FIG. 12 or 3 are omitted in FIG. 11. An equivalentcircuit of the SRAM memory cell having the layout configuration of thefourth preferred embodiment is similar to that of the third preferredembodiment described with respect to FIG. 10.

Referring to FIGS. 11, 12 and 3, description will proceed to the memorycell structure of the fourth preferred embodiment.

Of polysilicon wirings PL13 and PL17 (corresponding to the polysiliconwiring PL1 of the first preferred embodiment), which become the gate ofa NMOS transistor N1 and a PMOS transistor P1, the polysilicon wiringPL17 that becomes a resistance R1 is formed from a material having ahigher resistance than the polysilicon wiring PL13. For instance, whenthe polysilicon wiring PL13 is formed from CoSi, the polysilicon wiringPL17 is formed from a material having a higher resistivity than CoSi.

The polysilicon wiring PL17 is electrically connected through a gatecontact hole GC to an aluminum wiring AL12 that is a storage terminalNb.

Likewise, of polysilicon wirings PL14 and PL18 (corresponding to thepolysilicon wiring PL2 of the first preferred embodiment), which becomethe gate of a NMOS transistor N2 and a PMOS transistor P2, thepolysilicon wiring PL18 that becomes a resistance R2 is formed from amaterial having a higher resistance than the polysilicon wiring PL14.The polysilicon wiring PL18 is electrically connected through a gatecontact hole GC to an aluminum wiring AL11 that is a storage terminalNa. Otherwise, the configuration is similar to that of the firstpreferred embodiment described with respect to FIGS. 1 to 3, and thedescription thereof is thus omitted.

The fourth preferred embodiment having the foregoing memory cellstructure produces the following effect in addition to the first tosixth effects of the first preferred embodiment.

In the memory cell of the fourth preferred embodiment, the responsecharacteristic for inverting the data held in the cell is elongated dueto signal delay propagating the resistances R1 and R2. As a result, evenif the potential of one of the storage terminals Na and Nb is invertedby electrons generated from alpha rays and neutron beams, it returns tothe initial hold state before the data of the other storage terminal isinverted, thereby soft error becomes much rare.

Fifth Preferred Embodiment

FIGS. 13 to 15 are diagrams illustrating a memory cell structure of aSRAM according to a fifth preferred embodiment of the invention. FIG. 13is an explanatory diagram viewed from above the layout configuration inall layers. FIG. 14 is an explanatory diagram viewed from above mainlythe layout configuration over a second aluminum wiring layer in FIG. 13.An explanatory diagram viewed from above the layout configurationbeneath a first aluminum wiring layer in FIG. 13 is similar to that ofFIG. 2 in the first preferred embodiment, except that the word line WL2is divided into word lines WLA2 and WLB2. Some reference numerals usedin FIG. 14 or 2 are omitted in FIG. 13.

FIG. 15 is a circuit diagram illustrating an equivalent circuit of theSRAM memory cell having the layout configuration shown in FIGS. 13, 14and 2. Referring to FIG. 15, a word line WLA is connected to the gate ofa NMOS transistor N3, and a word line WLB that is independent of theword line WLA is connected to the gate of a NMOS transistor N4.Otherwise, the configuration is similar to that of the first preferredembodiment described with respect to FIG. 4, and the description thereofis thus omitted.

Referring to FIGS. 13, 14 and 2, description will proceed to the memorycell structure of the fifth preferred embodiment.

A polysilicon wiring PL3 is electrically connected through a gatecontact hole GC to a word line WLA1 (first layer aluminum wiring). Theword line WLA1 is electrically connected through a via hole 1T to a wordline WLA2 (second layer aluminum wiring). The word line WLA2 iselectrically connected through a via hole 2T to a word line WLA3 (thirdlayer aluminum wiring). The word line WLA of FIG. 15 is made up of theseword lines WLA1 to WLA3.

Likewise, a polysilicon wiring PL4 is electrically connected through agate contact hole GC to a word line WLB1 (first layer aluminum wiring).The word line WLB1 is electrically connected through a via hole 1T to aword line WLB2 (second layer aluminum wiring). The word line WLB2 iselectrically connected through a via hole 2T to a word line WLB3 (thirdlayer aluminum wiring). The word line WLB of FIG. 15 is made up of theseword lines WLB1 to WLB3.

The word line WLA3, WLB3 and a ground wiring LG3 are disposed parallelwith each other, across P well regions PW0, PW1 and an N well region NW.Two ground wirings LG3 are disposed with the word lines WLA3 and WLB3interposed therebetween. Otherwise, the layout configuration is similarto that of the first preferred embodiment, and the description thereofis thus omitted.

The fifth preferred embodiment having the foregoing memory cellstructure produces the following effect in addition to the first tosixth effects of the first preferred embodiment.

As shown in the equivalent circuit of FIG. 15, the word line connectedto the gate of the NMOS transistors N3 and N4 that are accesstransistors can be divided into the word lines WLA and WLB. This enablesto realize a memory cell structure usable in a FIFO memory.

Sixth Preferred Embodiment

FIGS. 16 to 18 are diagrams illustrating a memory cell structure of aSRAM according to a sixth preferred embodiment of the invention. FIG. 16is an explanatory diagram viewed from above the layout configuration inall layers. FIG. 17 is an explanatory diagram viewed from above mainlythe layout configuration beneath a first aluminum wiring layer in FIG.16. FIG. 18 is an explanatory diagram viewed from above the layoutconfiguration over a second aluminum wiring layer in FIG. 16. Somereference numerals used in FIG. 17 or 18 are omitted in FIG. 16. Anequivalent circuit of the SRAM memory cell having the layoutconfiguration of the sixth preferred embodiment is similar to that ofFIG. 15 described in the fifth preferred embodiment.

Referring to FIGS. 16 to 18, description will proceed to the memory cellstructure of the sixth preferred embodiment.

In an N⁺ diffusion region for NMOS transistors N3 and N4, the directionof formation of a source/drain region is located at an angle of 90° tothe direction of formation of a source/drain region of NMOS transistorsN1, N2 and PMOS transistors P1, P2. That is, diffusion regions FL242 andFL243 for the NMOS transistor N3, and diffusion regions FL232 and FL233for the NMOS transistor N4, are disposed in the lateral directionviewing the drawing.

A bit line BLB1 over the diffusion region FL243 is electricallyconnected through a diffusion contact hole 1C to the diffusion regionFL243. A bit line BLB2 (second layer aluminum wiring) is electricallyconnected through a via hole 1T to the bit line BLB1 (not shown in FIG.18).

Likewise, a bit line BLA1 over the diffusion region FL232 constitutingthe NMOS transistor N3 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL232. A bit line BLA2 (secondlayer aluminum wiring) is electrically connected through a via hole 1Tto the bit line BLA1 (not shown in FIG. 18).

The bit lines BLA2 and BLB2 are disposed parallel with each other,across P well regions PW0, PW1 and an N well region NW.

A ground wiring LG1 is electrically connected through a diffusioncontact hole 1C to diffusion regions FL210 and FL221. A ground wiringLG2 is electrically connected through a via hole 1T to the ground wiringLG1 (not shown in FIG. 18). A ground wiring LG3 is electricallyconnected through a via hole 2T to the ground wiring LG2.

A power supply wiring LV1 is electrically connected through a diffusioncontact hole 1C to diffusion regions FL110 and FL121. A power supplywiring LV2 is electrically connected through a via hole 1T to the powersupply wiring LV1 (not shown in FIG. 18). A power supply wiring LV3 iselectrically connected through a via hole 2T to the power supply wiringLV2.

A word line WLA1 is electrically connected through a gate contact holeGC to a polysilicon wiring PL23. A word line WLA2 is electricallyconnected through a via hole 1T to the word line WLA1 (not shown in FIG.18). A word line WLA3 (third layer aluminum wiring) is electricallyconnected through a via hole 2T to the word line WLA2.

Likewise, a word line WLB1 is electrically connected through a gatecontact hole GC to a polysilicon wiring PL24. A word line WLB2 iselectrically connected through a via hole 1T to the word line WLB1 (notshown in FIG. 18). A word line WLB3 (third layer aluminum wiring) iselectrically connected through a via hole 2T to the word line WLB2.

The (first) ground wiring LG3, word line WLB3, power supply wiring LV3,word line WLA3 and (second) ground wiring LG3 are disposed parallel witheach other in the longitudinal direction viewing the drawing. The(first) ground wiring LG3 and word line WLB3 are disposed over the Pwell region PW0. The power supply wiring LV3 is disposed over the N wellregion NW. The word line WLA3 and (second) ground wiring LG3 aredisposed over the P well region PW1.

The sixth preferred embodiment having the foregoing memory cellstructure produces the effect equivalent to that inherent in the fifthpreferred embodiment, in addition to the first to third, fifth and sixtheffects of the first preferred embodiment.

Seventh Preferred Embodiment

FIGS. 19 to 21 are diagrams illustrating a memory cell structure of aSRAM according to a seventh preferred embodiment of the invention. FIG.19 is an explanatory diagram viewed from above the layout configurationin all layers. FIG. 20 is an explanatory diagram viewed from abovemainly the layout configuration beneath a first aluminum wiring layer inFIG. 19. FIG. 21 is an explanatory diagram viewed from above the layoutconfiguration over a second aluminum wiring layer in FIG. 19. Somereference numerals used in FIG. 20 or 21 are omitted in FIG. 19. Anequivalent circuit of the SRAM memory cell having the layoutconfiguration of the seventh preferred embodiment is similar to that ofFIG. 4 in the first preferred embodiment.

Referring to FIGS. 19 to 21, description will proceed to the memory cellstructure of the seventh preferred embodiment.

A common polysilicon wiring PL5 of NMOS transistors N3 and N4 extendsover a P well region PW0, N well region NW and P well region PW1. Thecommon polysilicon wiring PL5 is used as the word line WL of FIG. 4.

Otherwise, the configuration is similar to that of the second preferredembodiment described with respect to FIGS. 5, 6 and 3, except for thepattern shape of polysilicon wirings PL1 and PL2, the position of a gatecontact hole GC between a polysilicon wiring PL1 and an aluminum wiringAL12, and the position of a gate contact hole GC between a polysiliconwiring PL2 and an aluminum wiring AL11.

The seventh preferred embodiment having the foregoing memory cellstructure produces the same effects as the second preferred embodiment.In addition, since the word line WL does not require any of via holes1T, 2T and word lines WL2, WL3, the number of necessary layers isreduced to lower the cost.

Eighth Preferred Embodiment

FIGS. 22 to 25 are diagrams illustrating a memory cell structure of aSRAM according to an eighth preferred embodiment of the invention. FIG.22 is an explanatory diagram viewed from above the layout configurationin all layers. FIG. 23 is an explanatory diagram viewed from abovemainly the layout configuration beneath a first aluminum wiring layer inFIG. 22. FIG. 24 is an explanatory diagram viewed from above the layoutconfiguration over a second aluminum wiring layer in FIG. 22. Somereference numerals used in FIG. 23 or 24 are omitted in FIG. 22.

FIG. 25 is a circuit diagram illustrating an equivalent circuit of theSRAM memory cell having the layout configuration shown in FIGS. 22 to24. Referring to FIG. 25, the SRAM memory cell of the eighth preferredembodiment is made up of NMOS transistors N1, N2, N5 to N8, and PMOStransistors P1 and P2.

The NMOS transistor N5 is interposed between a bit line BLA and astorage terminal Nb. The NMOS transistor N6 is interposed between a bitline BLA and a storage terminal Na. The gates of the NMOS transistors N5and N6 are both connected to a word line WLA.

The NMOS transistor N7 is interposed between a bit line BLB and astorage terminal Na. The NMOS transistor N8 is interposed between a bitline BLB and a storage terminal Nb. The gates of the NMOS transistors N7and N8 are both connected to a word line WLB.

The PMOS transistors P1 and P2 that are driver transistors are disposedwithin an N well region NW. The NMOS transistor N1 that is a drivertransistor and the NMOS transistors N7 and N8 that are accesstransistors are disposed within a P well region PW0. The NMOS transistorN2 that is a driver transistor and the NMOS transistors N5 and N6 thatare access transistors are disposed within a P well region PW1. The Pwell regions PW0 and PW1 are oppositely disposed with the N well regionNW interposed therebetween. Otherwise, the configuration is similar tothat of the equivalent circuit of FIG. 15 described in the fifthpreferred embodiment.

Referring to FIGS. 22 to 24, description will proceed to the memory cellstructure of the eighth preferred embodiment.

In the N well region NW, the PMOS transistor P1 is made up of P⁺diffusion regions FL110, FL111 and a polysilicon wiring PL17, and thePMOS transistor P2 is made up of P⁺ diffusion regions FL120, FL121 and apolysilicon wiring PL18.

In the P well region PW0, the NMOS transistor N1 is made up of N⁺diffusion regions FL212, FL213 and the polysilicon wiring PL17. The NMOStransistor N7 is made up of N⁺ diffusion regions FL244, FL245 and apolysilicon wiring PL20. The NMOS transistor N8 is made up of N⁺diffusion regions FL246, FL247 and the polysilicon wiring PL20. Thepolysilicon wiring PL17 extends from the N well region NW to the P wellregion PW0, so as to be used as a gate common to the NMOS transistor N1and PMOS transistor P1. The polysilicon wiring PL20 is common to theNMOS transistors N7 and N8.

In the P well region PW1, the NMOS transistor N2 is made up of N⁺diffusion regions FL222, FL223 and the polysilicon wiring PL18. The NMOStransistor N5 is made up of N⁺ diffusion regions FL234, FL235 and apolysilicon wiring PL19. The NMOS transistor N3 is made up of N⁺diffusion regions FL236, FL237 and a polysilicon wiring PL19. Thepolysilicon wiring PL18 extends from the N well region NW to the P wellregion PW1, so as to be used as a gate common to the NMOS transistor N2and PMOS transistor P2. The polysilicon wiring PL18 is common to theNMOS transistors N5 and N6. The foregoing diffusion regions areobtainable by implanting and diffusing impurity.

A ground wiring LG1 over the diffusion region FL212 is electricallyconnected through a diffusion contact hole 11C to the diffusion regionFL212. A bit line BLB1 over the diffusion region FL245 is electricallyconnected through a diffusion contact hole 1C to the diffusion regionFL245. A bit line BLB1 over the diffusion region FL247 is electricallyconnected through a diffusion contact hole 1C to the diffusion regionFL247.

An aluminum wiring AL15, which is a first layer aluminum wiringextending over the diffusion regions FL244, FL213, FL111 and FL237, iselectrically connected through a diffusion contact hole 1C to thediffusion regions FL244, FL213, FL111 and FL237, respectively. Thealuminum wiring AL15 is also disposed over part of the polysiliconwiring PL18, and is electrically connected through a gate contact holeGC to the polysilicon wiring PL18. The aluminum wiring AL15 can beelectrically connected with low impedance, and it corresponds to thestorage terminal Na.

A polysilicon wiring PL20 is electrically connected through a gatecontact hole GC to a word line WLB1.

A power supply wiring LV1 over the diffusion region FL110 iselectrically connected through a diffusion contact hole 1C to thediffusion region FL110. A power supply wiring LV1 over the diffusionregion FL121 is electrically connected through a diffusion contact hole1C to the diffusion region FL121.

The ground wiring LG1 is electrically connected through two diffusioncontact holes 1C to the diffusion region FL223. A bit line BLA1 over thediffusion region FL234 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL234. A bit line BLA1 over thediffusion region FL236 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL236.

An aluminum wiring AL16, which is a first layer aluminum wiringextending over the diffusion regions FL235, FL222, FL120 and FL246, iselectrically connected through a diffusion contact hole 1C to thediffusion regions FL235, FL222, FL120 and FL246, respectively. Thealuminum wiring AL16 is also disposed over part of the polysiliconwiring PL17, and is electrically connected through a gate contact holeGC to the polysilicon wiring PL17. The aluminum wiring AL16 can beelectrically connected with low impedance, and it corresponds to thestorage terminal Nb.

A word line WLA1 over a polysilicon wiring PL19 is electricallyconnected through a gate contact hole GC to the polysilicon wiring PL19.

A ground wiring LG1 is electrically connected through a via hole 1T to aground wiring LG2, and the ground wiring LG2 is electrically connectedthrough a via hole 2T to a ground wiring LG3.

The word line WLA1 is electrically connected through a via hole 1T to aword line WLA2, and the word line WLA2 is electrically connected througha via hole 2T to a word line WLA3. The word line WLA of FIG. 25 is madeup of these word lines WLA1 to WLA3.

Likewise, a word line WLB1 is electrically connected through a via hole1T to a word line WLB2, and the word line WLB2 is electrically connectedthrough a via hole 2T to a word line WLB3. The word line WLB of FIG. 25is made up of these word lines WLB1 to WLB3.

The word lines WLA3, WLB3, and ground wiring LG3 are disposed parallelwith each other, across the P well regions PW0, PW1, and the N wellregion NW. Two ground wirings LG3 are disposed with the word lines WLA3and WLB3 interposed therebetween.

A bit line BLA2 is electrically connected through a via hole 1T to a bitline BLA1, and a bit line BLB2 is electrically connected through a viahole 1T to a bit line BLB1.

Likewise, a bit line BLA2 is electrically connected through a via hole1T to a bit line BLA1, and a bit line BLB2 is electrically connectedthrough a via hole 1T to a bit line BLB1.

A power supply wiring LV2 is electrically connected through a via hole1T to a power supply wiring LV1. The bit lines BLA, BLA, BLB and BLB,are made up of the bit lines BLA1 and BLA2; BLA1 and BLA2; BLB1 andBLB2; and BLB1 and BLB2, respectively.

The paired bit lines BLA2 and BLA2, paired bit lines BLB2 and BLB2, andthe power supply wiring LV2 are disposed over the P well regions PW1,PW0 and N well region NW, respectively, so that these are parallel witheach other in the longitudinal direction viewing the drawing.

Thus, in the memory cell structure of the SRAM of the eighth preferredembodiment, with the N well region NW interposed between the P wellregions PW0 and PW1, the NMOS transistors N1, N7 and N8 are disposed inthe P well region PW0, and the NMOS transistors N2, N5 and N6 aredisposed in the P well region PW1. Thereby, the N⁺ diffusion regionFL213 and the N⁺ diffusion region FL222 that are electrically connectedto the storage terminals Na and Nb, respectively, can be separatelyformed in the different P well regions PW0 and PW1.

As a result, it is able to increase resistance to soft error, which isthe first effect of the first preferred embodiment.

Since the P well regions PW0 and PW1 are separately formed in adirection vertical to the direction of formation of the paired bit linesBLA and BLA, and the paired bit lines BLB and BLB, the formation of thetwo P well regions PW0 and PW1 exerts no influence on the wiring lengthof the paired bit lines BLA and BLA, and the paired bit lines BLB andBLB. Hence, there is no possibility that the formation of the P wellregions PW0 and PW1 increases the wiring length of the bit lines, thusmaintaining a good access time. This corresponds to the second effect ofthe first preferred embodiment.

Since the NMOS transistors N1 and N2, the NMOS transistors N5 and N7,and the NMOS transistors N6 and N8, are respectively arranged so as tobe point symmetry with respect to the central part of the memory cell(the central part of the N well region NW), the degree of integrationcan be increased when a plurality of the memory cells of the eighthpreferred embodiment are disposed adjacent each other. This correspondsto the third effect of the first preferred embodiment.

The formation of the polysilicon wirings PL17 to PL20 in the samedirection (the lateral direction viewing the drawing) facilitates thecontrol of the gate dimension. Further, since the polysilicon wiringsPL17 and PL19, and the polysilicon wirings PL18 and PL20, arerespectively arranged in a straight line, no waste region is present anda reduction in the circuit area increases the degree of integration.This corresponds to the fourth effect of the first preferred embodiment.

By separately forming a region serving as a drain in the NMOStransistors N1, N2 and N5 to N8, resistance to soft error can bemaintained at a high level. This corresponds to the fifth effect of thefirst preferred embodiment.

With the arrangement such that each of inverters I1 and I2 of a CMOSstructure is made up of a combination of a NMOS transistor and a PMOStransistor, the memory cell can be realized by at least sufficientcircuit configuration as a CMOS structure. This corresponds to the sixtheffect of the first preferred embodiment.

In addition, the memory cell of the eighth preferred embodiment realizesa two-port memory cell which employs two word lines WLA and WLB, and twopairs of bit lines (the paired bit lines BLA and BLA, and paired bitlines BLB and BLB), as shown in FIG. 25.

Ninth Preferred Embodiment

FIGS. 26 to 28 are diagrams illustrating a memory cell structure of aSRAM according to a ninth preferred embodiment of the invention. FIG. 26is an explanatory diagram viewed from above the layout configuration inall layers. FIG. 27 is an explanatory diagram viewed from above mainlythe layout configuration beneath a first aluminum wiring layer in FIG.26. FIG. 28 is an explanatory diagram viewed from above the layoutconfiguration over a second aluminum wiring layer in FIG. 26. Somereference numerals used in FIG. 27 or 28 are omitted in FIG. 26.

An equivalent circuit of the SRAM memory cell having the layoutconfiguration of the ninth preferred embodiment is similar to that ofFIG. 25 in the eighth preferred embodiment.

Referring to FIGS. 26 to 28, the memory cell structure of the ninthpreferred embodiment will be described particularly with regard to thedifferent points from the eighth preferred embodiment.

In a P well region PW0, a NMOS transistor N1 is made up of N⁺ diffusionregions FL214, FL215 and a polysilicon wiring PL31. Here, a considerablylarge gate width than that of other NMOS transistors N5 to N8 can be setby forming the polysilicon wiring PL31 by bending it 90° two times overthe N⁺ diffusion regions (FL214, FL215) for the NMOS transistor N1.

The NMOS transistor N7 is made up of N⁺ diffusion regions FL270, FL271and a polysilicon wiring PL37. The NMOS transistor N8 is made up of N⁺diffusion regions FL280, FL281 and a polysilicon wiring PL38.

The polysilicon wiring PL31 extends from an N well region NW to the Pwell region PW0, so as to be used as a gate common to the NMOStransistor N1 and a PMOS transistor P1.

In a P well region PW1, the NMOS transistor N2 is made up of N⁺diffusion regions FL224, FL225 and a polysilicon wiring PL32. Here, aconsiderably large gate width than that of the other NMOS transistors N5to N8 can be set by forming the polysilicon wiring PL32 by bending it90° two times over the N⁺ diffusion regions (FL224, FL225) for the NMOStransistor N2.

The NMOS transistor N5 is made up of N⁺ diffusion regions FL250, FL251and a polysilicon wiring PL35. The NMOS transistor N6 is made up of N⁺diffusion regions FL260, FL261 and a polysilicon wiring PL36.

The polysilicon wiring PL32 extends from the N well region NW to the Pwell region PW0, so as to be used as a gate common to the NMOStransistor N2 and a PMOS transistor P2. The foregoing diffusion regionsare obtainable by implanting and diffusing impurity.

Each of two ground wirings LG1 over the diffusion region FL214 iselectrically connected through a diffusion contact hole 1C to thediffusion region FL214. A bit line BLB1 over the diffusion region FL271is electrically connected through a diffusion contact hole 1C to thediffusion region FL271. A bit line BLB1 over the diffusion region FL280is electrically connected through a diffusion contact hole 1C to thediffusion region FL280.

An aluminum wiring AL17, which is a first layer aluminum wiringextending over the diffusion regions FL281, FL215, FL111, and FL251, iselectrically connected through a diffusion contact hole 1C to thediffusion regions FL281, FL215, FL111 and FL251, respectively. Thealuminum wiring AL17 is also disposed over part of the polysiliconwiring PL32, and is electrically connected through a gate contact holeGC to the polysilicon wiring PL32. The aluminum wiring AL17 can beelectrically connected with low impedance, and it corresponds to astorage terminal Na.

The polysilicon wirings PL37 and PL38 are both electrically connectedthrough a gate contact hole GC to a word line WLB1.

A power supply wiring LV1 over the diffusion region FL110 iselectrically connected through a diffusion contact hole 1C to thediffusion region FL110. A power supply wiring LV1 over the diffusionregion FL121 is electrically connected through a diffusion contact hole1C to the diffusion region FL121.

Each of two ground wirings LG1 over the diffusion region FL224 iselectrically connected through a diffusion contact hole 1C to thediffusion region FL224. A bit line BLA1 over the diffusion region FL250is electrically connected through a diffusion contact hole 1C to thediffusion region FL250. A bit line BLA1 over the diffusion region FL261is electrically connected through a diffusion contact hole 1C to thediffusion region FL261.

An aluminum wiring AL18, which is a first layer aluminum wiringextending over the diffusion regions FL260, FL224, FL120 and FL270, iselectrically connected through a diffusion contact hole 1C to thediffusion regions FL260, FL224, FL120 and FL270, respectively. Thealuminum wiring AL18 is also disposed over part of the polysiliconwiring PL31, and is electrically connected through a gate contact holeGC to the polysilicon wiring PL31. The aluminum wiring AL18 can beelectrically connected with low impedance, and it corresponds to astorage terminal Nb.

A word line WLA1 over the polysilicon wirings PL35 and PL36 iselectrically connected through a gate contact hole GC to the polysiliconwirings PL35 and PL36, respectively.

A ground wiring LG1 is electrically connected through a via hole 1T to aground wiring LG2, and the ground wiring LG2 is electrically connectedthrough a via hole 2T to a ground wiring LG3.

A word line WLA1 is electrically connected through a via hole 1T to aword line WLA2, and the word line WLA2 is electrically connected througha via hole 2T to a word line WLA3. Likewise, a word line WLB1 iselectrically connected through a via hole 1T to a word line WLB2, andthe word line WLB2 is electrically connected through a via hole 2T to aword line WLB3.

A bit line BLA2 is electrically connected through a via hole 1T to a bitline BLA1. A bit line BLB2 is electrically connected through a via hole1T to a bit line BLB1.

Likewise, a bit line BLA2 is electrically connected through a via hole1T to a bit line BLA1, and a bit line BLB2 is electrically connectedthrough a via hole 1T to a bit line BLB1. A power supply wiring LV2 iselectrically connected through a via hole 1T to a power supply wiringLV1.

Thus, in the memory cell structure of the SRAM of the ninth preferredembodiment, with the N well region NW interposed between the P wellregions PW0 and PW1, the NMOS transistors N1, N7 and N8 are disposed inthe P well region PW0, and the NMOS transistors N2, N5 and N6 aredisposed in the P well region PW1. This enables to increase resistanceto soft error, which is the first effect of the first preferredembodiment.

By separately forming the P well regions PW0 and PW1 in a directionvertical to the direction of formation of the paired bit lines BLA andBLA and the paired bit lines BLB and BLB, it is able to maintain a goodaccess time, which is the second effect of the first preferredembodiment.

Further, in the ninth preferred embodiment, as in the eighth preferredembodiment, the NMOS transistors N1 and N2, the NMOS transistors N5 andN7, and the NMOS transistors N6 and N8, are respectively arranged so asto be point symmetry with respect to the central part of the memorycell. It is therefore able to increase the degree of integration when aplurality of the memory cells of the ninth preferred embodiment aredisposed adjacent each other. This corresponds to the third effect ofthe first preferred embodiment.

Furthermore, by separately forming a region serving as a drain in theNMOS transistors N1, N2 and N5 to N8, resistance to soft error can bemaintained at a high level. This corresponds to the fifth effect of thefirst preferred embodiment.

By arranging such that each of inverters I1 and I2 of a CMOS structureis made up of a combination of a NMOS transistor and a PMOS transistor,the memory cell can be realized by at least sufficient circuitconfiguration as a CMOS structure. This corresponds to the sixth effectof the first preferred embodiment.

Like the eighth preferred embodiment, the memory cell of the ninthpreferred embodiment can be used as a two-port memory cell.

Additionally, as in the second preferred embodiment, it is able toincrease the operation speed and the stability of the memory cell byincreasing the gate width (channel width) of the NMOS transistors N1 andN2, each being a driver transistor.

Tenth Preferred Embodiment

FIGS. 29 to 31 are diagrams illustrating a memory cell structure of aSRAM according to a tenth preferred embodiment of the invention. FIG. 29is an explanatory diagram viewed from above the layout configuration inall layers. FIG. 30 is an explanatory diagram viewed from above mainlythe layout configuration beneath a first aluminum wiring layer in FIG.29. FIG. 31 is an explanatory diagram viewed from above the layoutconfiguration over a second aluminum wiring layer in FIG. 29. Somereference numerals used in FIG. 30 or 31 are omitted in FIG. 29.

An equivalent circuit of the SRAM memory cell having the layoutconfiguration of the tenth preferred embodiment is similar to that ofFIG. 25 in the eighth preferred embodiment.

Referring to FIGS. 29 to 31, description will proceed to the memory cellstructure of the tenth preferred embodiment.

In an N well region NW, a PMOS transistor P1 is made up of P⁺ diffusionregions FL110, FL111 and a polysilicon wiring PL41, and a PMOStransistor P2 is made up of P⁺ diffusion regions FL120, FL121 and apolysilicon wiring PL42.

In a P well region PW0, a NMOS transistor N1 is made up of N⁺ diffusionregions FL210, FL211 and the polysilicon wiring PL41, a NMOS transistorN7 is made up of N⁺ diffusion regions FL270, FL271 and a polysiliconwiring PL47, and a NMOS transistor N8 is made up of N⁺ diffusion regionsFL280, FL281 and the polysilicon wiring PL47. The polysilicon wiringPL41 extends from the N well region NW to the P well region PW0, so asto be used as a gate common to the NMOS transistor N1 and PMOStransistor P1. The polysilicon wiring PL47 is common to the NMOStransistors N7 and N8.

In a P well region PW1, a NMOS transistor N2 is made up of N⁺ diffusionregions FL220, FL221 and the polysilicon wiring PL42, a NMOS transistorN5 is made up of N⁺ diffusion regions FL250, FL251 and a polysiliconwiring PL45, and a NMOS transistor N6 is made up of N⁺ diffusion regionsFL260, FL261 and the polysilicon wiring PL45. The polysilicon wiringPL42 extends from the N well region NW to the P well region PW1, so asto be used as a gate common to the NMOS transistor N2 and PMOStransistor P2. The polysilicon wiring PL42 is common to the NMOStransistors N5 and N6. The foregoing diffusion regions are obtainable byimplanting and diffusing impurity.

A ground wiring LG1 over the diffusion region FL210 is electricallyconnected through a diffusion contact hole 1C to the diffusion regionFL210. A bit line BLB1 over the diffusion region FL271 is electricallyconnected through a diffusion contact hole 1C to the diffusion regionFL271. A bit line BLB1 over the diffusion region FL281 is electricallyconnected through a diffusion contact hole 1C to the diffusion regionFL281.

An aluminum wiring AL17, which is a first layer aluminum wiringextending over the diffusion region FL270 (FL211) and the diffusionregion FL111, is electrically connected through a diffusion contact hole1C to the diffusion regions FL270 (FL211) and FL111, respectively.

The aluminum wiring AL17 is also electrically connected to thepolysilicon wiring PL42. The polysilicon wiring PL42 is electricallyconnected through a shared contact SC to the diffusion regions FL111 andFL261, respectively. As used herein, the term “shared contact” means acommon contact electrically connecting a diffusion region andpolysilicon.

The aluminum wiring AL17 can be electrically connected with lowimpedance. The aluminum wiring AL17, two shared contacts SC andpolysilicon wiring PL42 correspond to a storage terminal Na.

The polysilicon wiring PL47 is electrically connected through a gatecontact hole GC to a word line WLB1.

A power supply wiring LV1 over the diffusion region FL110 iselectrically connected through a diffusion contact hole 1C to thediffusion region FL110. A power supply wiring LV1 over the diffusionregion FL121 is electrically connected through a diffusion contact hole1C to the diffusion region FL121.

A ground wiring LG1 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL221. A bit line BLA1 over thediffusion region FL250 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL250. A bit line BLA1 over thediffusion region FL260 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL260.

An aluminum wiring AL18, which is a first layer aluminum wiringextending over the diffusion region FL251 (FL220) and the diffusionregion FL120, is electrically connected through a diffusion contact hole1C to the diffusion regions FL251 (FL220).

The aluminum wiring AL18 is also electrically connected to thepolysilicon wiring PL41. The polysilicon wiring PL41 is electricallyconnected through a shared contact SC to the diffusion regions FL120 andFL280, respectively.

The aluminum wiring AL18 can be electrically connected with lowimpedance. The aluminum wiring AL18, two shared contacts SC andpolysilicon wiring PL41 correspond to a storage terminal Nb.

A word line WLA1 over the polysilicon wiring PL45 is electricallyconnected through a gate contact hole GC to the polysilicon wiring PL45.

A word line WLA1 is electrically connected through a via hole 1T to aword line WLA2, and the word line WLA2 is electrically connected througha via hole 2T to a word line WLA3. Likewise, a word line WLB1 iselectrically connected through a via hole 1T to a word line WLB2, andthe word line WLB2 is electrically connected through a via hole 2T to aword line WLB3.

The word lines WLA3 and WLB3 are disposed parallel with each other,across the P well regions PW0, PW1, and the N well region NW.

A bit line BLA2 is electrically connected through a via hole 1T to a bitline BLA1. A bit line BLB2 is electrically connected through a via hole1T to a bit line BLB1.

Likewise, a bit line BLA2 is electrically connected through a via hole1T to a bit line BLA1. A bit line BLB2 is electrically connected througha via hole 1T to a bit line BLB1.

A power supply wiring LV2 is electrically connected through a via hole1T to a power supply wiring LV1. A ground wiring LG1 is electricallyconnected through a via hole 1T to a ground wiring LG2.

The paired bit lines BLA2 and BLA2, paired bit lines BLB2 and BLB2,ground wiring LG2 and power supply wiring LV2 are disposed parallel witheach other in the longitudinal direction viewing the drawing.

The paired bit lines BLA2 and BLA2 and the ground wiring LG2 aredisposed over the P well region PW1. The paired bit lines BLB2 and BLB2and the ground wiring LG2 are disposed over the P well region PW0. Thepower supply wiring LV2 is disposed over the N well region NW.

Thus, in the memory cell structure of the SRAM of the tenth preferredembodiment, with the N well region NW interposed between the P wellregions PW0 and PW1, the NMOS transistors N1, N7 and N8 are disposed inthe P well region PW0, and the NMOS transistors N2, N5 and N6 aredisposed in the P well region PW1. This enables to increase resistanceto soft error, which is the first effect of the first preferredembodiment.

By separately forming the P well regions PW0 and PW1 in a directionvertical to the direction of formation of the paired bit lines BLA andBLA and the paired bit lines BLB and BLB, it is able to maintain a goodaccess time, which is the second effect of the first preferredembodiment.

Further, in the tenth preferred embodiment as in the eighth preferredembodiment, the NMOS transistors N1 and N2, the NMOS transistors N5 andN7, and the NMOS transistors N6 and N8, are respectively arranged so asto be point symmetry with respect to the central part of the memorycell. It is therefore able to increase the degree of integration when aplurality of the memory cells of the tenth preferred embodiment aredisposed adjacent each other. This corresponds to the third effect ofthe first preferred embodiment.

The memory cell of the tenth preferred embodiment realizes a two-portmemory cell, as in the eighth preferred embodiment.

The formation of the polysilicon wirings PL41, PL42, PL47 and PL48 inapproximately the same direction (the lateral direction viewing thedrawing) facilitates the control of the gate dimension. Further, becausethe polysilicon wirings PL41 and PL45, and the polysilicon wirings PL42and PL47, are respectively disposed in a straight line, no waste regionis present and a reduction in the circuit area increases the degree ofintegration. This corresponds to the fourth effect of the firstpreferred embodiment.

By arranging such that each of inverters I1 and I2 of a CMOS structureis made up of a combination of a NMOS transistor and a PMOS transistor,the memory cell can be realized by at least sufficient circuitconfiguration as a CMOS structure. This corresponds to the sixth effectof the first preferred embodiment.

In addition, with the arrangement that the storage terminal Na is madeup of the aluminum wiring AL17, shared contacts SC and polysiliconwiring PL42, and the storage terminal Nb is made up of the aluminumwiring AL18, shared contacts SC and polysilicon wiring PL41, it is ableto increase the degree of integration by the amount that the wellforming width in the longitudinal direction viewing the drawing can beformed by a two-transistor pitch.

Eleventh Preferred Embodiment

FIGS. 32 to 34 are diagrams illustrating a memory cell structure of aSRAM according to an eleventh preferred embodiment of the invention.FIG. 32 is an explanatory diagram viewed from above the layoutconfiguration in all layers. FIG. 33 is an explanatory diagram viewedfrom above mainly the layout configuration beneath a first aluminumwiring layer in FIG. 32. FIG. 34 is an explanatory diagram viewed fromabove the layout configuration over a second aluminum wiring layer inFIG. 32. Some reference numerals used in FIG. 33 or 34 are omitted inFIG. 32.

An equivalent circuit of the SRAM memory cell having the layoutconfiguration of the eleventh preferred embodiment is similar to that ofFIG. 4 in the first preferred embodiment.

Referring to FIGS. 32 to 34, description will proceed to the memory cellstructure of the eleventh preferred embodiment.

In an N well region NW, a PMOS transistor P1 is made up of P⁺ diffusionregions FL110, FL111 and a polysilicon wiring PL51, and a PMOStransistor P2 is made up of P⁺ diffusion regions FL120, FL121 and apolysilicon wiring PL52.

In a P well region PW0, a NMOS transistor N1 is made up of N⁺ diffusionregions FL210 (FL210A, FL210B), FL211 and the polysilicon wiring PL51,and a NMOS transistor N4 is made up of N⁺ diffusion regions FL240, FL241and a polysilicon wiring PL54. The polysilicon wiring PL51 extends fromthe N well region NW to the P well region PW0, so as to be used as agate common to the NMOS transistor N1 and PMOS transistor P1.

In a P well region PW1, a NMOS transistor N2 is made up of N⁺ diffusionregions FL220 (FL220A, FL220B), FL221 and the polysilicon wiring PL52,and a NMOS transistor N3 is made up of N⁺ diffusion regions FL230, FL231and a polysilicon wiring PL53. The polysilicon wiring PL52 extends fromthe N well region NW to the P well region PW1, so as to be used as agate common to the NMOS transistor N2 and PMOS transistor P2. Theforegoing diffusion regions are obtainable by implanting and diffusingimpurity.

A ground wiring LG1 over the diffusion region FL210A and FL210B iselectrically connected through a diffusion contact hole 1C to thediffusion region FL210A and FL210B, respectively. A bit line BLB1 overthe diffusion region FL241 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL241.

An aluminum wiring AL17, which is a first layer aluminum wiringextending over the diffusion region FL211 and the diffusion regionFL111, is electrically connected through a diffusion contact hole 1C tothe diffusion region FL211.

The aluminum wiring AL17 is also electrically connected to thepolysilicon wiring PL52. The polysilicon wiring PL52 is electricallyconnected through a shared contact SC to the diffusion regions FL111 andFL231, respectively.

The aluminum wiring AL17 can be electrically connected with lowimpedance. The aluminum wiring AL17, two shared contacts SC andpolysilicon wiring PL52 correspond to a storage terminal Na.

The polysilicon wiring PL54 is electrically connected through a gatecontact hole GC to a word line WL1.

A power supply wiring LV1 over the diffusion region FL110 iselectrically connected through a diffusion contact hole 1C to thediffusion region FL110. A power supply wiring LV1 over the diffusionregion FL121 is electrically connected through a diffusion contact hole1C to the diffusion region FL121.

A ground wiring LG1 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL221. A bit line BLA1 over thediffusion region FL230 is electrically connected through a diffusioncontact hole 1C to the diffusion region FL230.

An aluminum wiring AL18, which is a first layer aluminum wiringextending over the diffusion region FL220 and the diffusion regionFL120, is electrically connected through a diffusion contact hole 1C tothe diffusion region FL220.

The aluminum wiring AL18 is also electrically connected to thepolysilicon wiring PL51. The polysilicon wiring PL51 is electricallyconnected through a shared contact SC to the diffusion regions FL120 andFL240, respectively.

The aluminum wiring AL18 can be electrically connected with lowimpedance. The aluminum wiring AL18, two shared contacts SC andpolysilicon wiring PL51 correspond to a storage terminal Nb.

A word line WL1 over the polysilicon wiring PL53 is electricallyconnected through a gate contact hole GC to the polysilicon wiring PL53.

A word line WL1 is electrically connected through a via hole 1T to aword line WL2, and the word line WL2 is electrically connected through avia hole 2T to a word line WL3. The word line WL3 is disposed across theP well regions PW0, PW1 and the N well region NW.

A bit line BLA2 is electrically connected through a via hole 1T to a bitline BLA1. A bit line BLB2 is electrically connected through a via hole1T to a bit line BLB1.

A power supply wiring LV2 is electrically connected through a via hole1T to a power supply wiring LV1. A ground wiring LG1 is electricallyconnected through a via hole 1T to a ground wiring LG2.

The bit lines BLA2, BLB2, ground wiring LG2 and power supply wiring LV2are disposed parallel with each other in the longitudinal directionviewing the drawing.

The bit lines BLA2 and ground wiring LG2 are disposed over the P wellregion PW1. The bit lines BLB2 and ground wiring LG2 are disposed overthe P well region PW0. The power supply wiring LV2 is disposed over theN well region NW.

Thus, in the memory cell structure of the SRAM of the eleventh preferredembodiment, with the N well region NW interposed between the P wellregions PW0 and PW1, the NMOS transistors N1 and N4 are disposed in theP well region PW0, and the NMOS transistors N2 and N3 are disposed inthe P well region PW1. This enables to increase resistance to softerror, which is the first effect of the first preferred embodiment.

By separately forming the P well regions PW0 and PW1 in a directionvertical to the direction of formation of the bit lines BLA and BLB, itis able to maintain a good access time, which is the second effect ofthe first preferred embodiment.

Further, in the eleventh preferred embodiment, as in the first preferredembodiment, the NMOS transistors N1 and N2, and the NMOS transistors N3and N4, are respectively arranged so as to be point symmetry withrespect to the central part of the memory cell. It is therefore able toincrease the degree of integration when a plurality of the memory cellsof the eleventh preferred embodiment are disposed adjacent each other.This corresponds to the third effect of the first preferred embodiment.

The formation of the polysilicon wirings PL51 to PL54 in approximatelythe same direction (the lateral direction viewing the drawing)facilitates the control of the gate dimension. Further, because thepolysilicon wirings PL51 and PL53, and the polysilicon wirings PL52 andPL54, are respectively disposed in a straight line, no waste region ispresent and a reduction in the circuit area increases the degree ofintegration. This corresponds to the fourth effect of the firstpreferred embodiment.

By separately forming a region serving as a drain in the NMOStransistors N1 to N4, resistance to soft error can be maintained at ahigh level. This corresponds to the fifth effect of the first preferredembodiment.

With the arrangement such that each of inverters I1 and I2 of a CMOSstructure is made up of a combination of a NMOS transistor and a PMOStransistor, the memory cell can be realized by at least sufficientcircuit configuration as a CMOS structure. This corresponds to the sixtheffect of the first preferred embodiment.

In addition, with the arrangement that the storage terminal Na is madeup of the aluminum wiring AL17, shared contacts SC and polysiliconwiring PL52, and the storage terminal Nb is made up of the aluminumwiring AL18, shared contacts SC and polysilicon wiring PL51, it is ableto increase the degree of integration by the amount that the wellforming width in the longitudinal direction viewing the drawing can beformed by a two-transistor pitch.

Twelfth Preferred Embodiment

FIGS. 35 and 36 are diagrams illustrating a memory cell structure of aSRAM according to a twelfth preferred embodiment of the invention. FIG.35 is an explanatory diagram viewed from above the layout configurationin all layers. FIG. 36 is an explanatory diagram viewed from abovemainly the layout configuration over a second aluminum wiring layer inFIG. 35. An explanatory diagram viewed from above the layoutconfiguration beneath a first aluminum wiring layer in FIG. 35 issimilar to that of FIG. 33 described in the eleventh preferredembodiment, except that the word line WL2 is divided into word linesWLA2 and WLB2. Some reference numerals used in FIG. 36 or 33 are omittedin FIG. 35. An equivalent circuit of the SRAM memory cell having thelayout configuration of the twelfth preferred embodiment is similar tothat of FIG. 15 in the fifth preferred embodiment.

Referring to FIGS. 35, 36 and 33, description will proceed to the memorycell structure of the twelfth preferred embodiment.

A polysilicon wiring PL53 is electrically connected through a gatecontact hole GC to a word line WLA1 (corresponding to the word line WL1at the right end in FIG. 33). The word line WLA1 is electricallyconnected through a via hole 1T to the word line WLA2. The word lineWLA2 is electrically connected through a via hole 2T to a word lineWLA3. The word line WLA of FIG. 15 is made up of these word lines WLA1to WLA3.

Likewise, a polysilicon wiring PL54 is electrically connected through agate contact hole GC to a word line WLB1 (corresponding to the word lineWL1 at the left end in FIG. 33). The word line WLB1 is electricallyconnected through a via hole 1T to a word line WLB2. The word line WLB2is electrically connected through a via hole 2T to a word line WLB3. Theword line WLB of FIG. 15 is made up of these word lines WLB1 to WLB3.

The word lines WLA3 and WLB3 are disposed parallel with each other,across P well regions PW0, PW1 and an N well region NW. Otherwise, thelayout configuration is similar to that of the eleventh preferredembodiment, and the description thereof is thus omitted.

The twelfth preferred embodiment having the foregoing memory cellstructure produces the effects of the eleventh preferred embodiment, andalso realizes a memory cell structure usable in FIFO memory, as in thefifth preferred embodiment.

Other Embodiments

If every conductivity type is reversed in the foregoing first to twelfthpreferred embodiments, the same effects are obtainable. Further, theseembodiments are applicable with the same effects to field effecttransistors such as MIS transistors, without limiting to MOStransistors.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

What is claimed is:
 1. A semiconductor memory comprising: a memory cellhaving first and second storage terminals storing information of logiclevels complementary to each other; a power supply wiring supplying apredetermined power supply voltage to said memory cell; first and secondpairs of bit lines each electrically connected to said first and secondstorage terminals of said memory cell, when selected; and first andsecond word lines connected to said memory cell, said first pair of bitlines connected to said memory cell and at least reading out data storedat said first and second storage terminals from said memory cell inresponse to a signal on said first word line, and said second pair ofbit lines connected to said memory cell and at least reading out datastored at said first and second storage terminals from said memory cellin response to a signal on said second word line, wherein said first andsecond pairs of bit lines and said power supply wiring are provided inparallel to each other, with said power supply wiring interposed betweensaid first and second pairs of bit lines.
 2. The semiconductor memoryaccording to claim 1, further comprising: first and second groundwirings each supplying a predetermined ground potential to said memorycell, wherein said first pair of bit lines and said first ground wiringare provided in parallel to each other, with said first ground wiringinterposed between said first pair of bit lines, and said second pair ofbit lines and said second ground wiring are provided in parallel to eachother, with said second ground wiring interposed between said secondpair of bit lines.
 3. The semiconductor memory according to claim 1,wherein said memory cell is formed on first and second P wells and an Nwell interposed between said first and second P wells in a firstdirection, and said power supply wiring extending along a seconddirection vertical to said first direction is formed on said N well. 4.A semiconductor device having a two-port type static random accessmemory, one memory cell of which includes first and second inverters,the first inverter comprises first and third transistors and the secondinverter comprises second and fourth transistors, comprising: first andsecond well regions of a first conductivity type; a third well region ofa second conductivity type disposed between the first and second wellregions in a plane view; a first pair of impurity regions of the firstconductivity type provided in the third well region, functioning as twoelectrodes of the first transistor; a second pair of impurity regions ofthe first conductivity type provided in the third well region,functioning as two electrodes of the second transistor; a third pair ofimpurity regions of the second conductivity type provided in the firstwell region, functioning as two electrodes of the third transistor; afourth pair of impurity regions of the second conductivity type providedin the first well region, functioning as two electrodes of the fourthtransistor; a fifth pair of impurity regions of the second conductivitytype provided in the first well region, functioning as two electrodes ofa fifth transistor; a sixth pair of impurity regions of the secondconductivity type provided in the second well region, functioning as twoelectrodes of a sixth transistor; a seventh pair of impurity regions ofthe second conductivity type provided in the second well region,functioning as two electrodes of a seventh transistor; an eighth pair ofimpurity regions of the second conductivity type provided in the secondwell region, functioning as two electrodes of an eighth transistor; afirst conductive layer provided over the first and third well regions,functioning as a gate electrode common to the first and thirdtransistors; a second conductive layer provided over the second andthird well regions, functioning as a gate electrode common to the secondand fourth transistors; a third conductive layer provided over the firstwell region, functioning as a gate electrode common to the fifth andsixth transistors; a fourth conductive layer provided over the secondwell region, functioning as a gate electrode common to the seventh andeighth transistors; a fifth conductive layer electrically connected tothe second conductive layer, one of the first pair of impurity regions,one of the third pair of impurity regions, one of the fifth pair ofimpurity regions and one of the eighth pair of impurity regions, andfunctioning as one storage terminal of the one memory cell; a sixthconductive layer electrically connected to the first conductive layer,one of the second pair of impurity regions, one of the fourth pair ofimpurity regions, one of the seventh pair of impurity regions and one ofthe sixth pair of impurity regions, and functioning as another storageterminal of the one memory cell; a first word line electricallyconnected to the third conductive layer; a second word line electricallyconnected to the fourth conductive layer; a first bit line electricallyconnected to the other of the fifth pair of impurity regions; a secondbit line electrically connected to the other of the sixth pair ofimpurity regions; a third bit line electrically connected to the otherof the seventh pair of impurity regions; and a fourth bit lineelectrically connected to the other of the eighth pair of impurityregions.
 5. The semiconductor device according to claim 4, wherein afirst supply voltage is supplied to the other of the first pair ofimpurity regions and the other of the second pair of impurity regions,and a second supply voltage is supplied to the other of the third pairof impurity regions and the other of the fourth pair of impurityregions.
 6. The semiconductor device according to claim 4, wherein theones of the third and fifth pairs of impurity regions are a commonimpurity region, and the ones of the fourth and seventh pairs ofimpurity regions are a common impurity region.
 7. The semiconductordevice according to claim 4, wherein the one of the first pair ofimpurity regions is electrically connected to the fifth conductive layervia a first contact hole disposed between overlapped portions of thefifth conductive layer and the one of the first pair of impurity regionsin the plane view, the one of the third pair of impurity regions iselectrically connected to the fifth conductive layer via a secondcontact hole disposed between overlapped portions of the fifthconductive layer and the one of the third pair of impurity regions inthe plane view, the one of the eighth pair of impurity regions iselectrically connected to the fifth conductive layer via a third contacthole disposed between overlapped portions of the fifth conductive layerand the one of the eighth impurity regions in the plane view, the one ofthe second pair of impurity regions is electrically connected to thesixth conductive layer via a fourth contact hole disposed betweenoverlapped portions of the sixth conductive layer and the one of thesecond pair of impurity regions in the plane view, the one of the fourthpair of impurity regions is electrically connected to the sixthconductive layer via a fifth contact hole disposed between overlappedportions of the sixth conductive layer and the one of the sixth pair ofimpurity regions in the plane view, and the one of the sixth pair ofimpurity regions is electrically connected to the sixth conductive layervia a sixth contact hole disposed between overlapped portions of thesixth conductive layer and the one of the fifth pair of impurity regionsin the plane view.
 8. The semiconductor device according to claim 4,wherein the second conductive layer is electrically connected to thefifth conductive layer via a seventh contact hole disposed betweenoverlapped portions of the second and fifth conductive layers in theplane view, and the first conductive layer is electrically connected tothe sixth conductive layer via an eighth contact hole disposed betweenoverlapped portions of the first and sixth conductive layers in theplane view.
 9. The semiconductor device according to claim 4, whereinthe one of the first pair of impurity regions and the second conductivelayer are electrically connected to the fifth conductive layer via afirst shared contact disposed between overlapped portions of the fifthconductive layer and the one of the first pair of impurity regions inthe plane view, the one of the third pair of impurity regions is animpurity region common to the one of the fourth pair of impurityregions, and is electrically connected to the fifth conductive layer viaa first contact hole disposed between overlapped portions of the fifthconductive layer and the one of the third pair of impurity regions inthe plane view, the one of the eighth pair of impurity regions iselectrically connected to the second conductive layer via a secondshared contact, the one of the second pair of impurity regions and thefirst conductive layer are electrically connected to the sixthconductive layer via a third shared contact disposed between overlappedportions of the sixth conductive layer and the one of the second pair ofimpurity regions in the plane view, the one of the fourth pair ofimpurity regions is an impurity region common to the one of the seventhpair of impurity regions, and is electrically connected to the sixthconductive layer via a second contact hole disposed between overlappedportions of the sixth conductive layer and the one of the sixth impurityregions in the plane view, and the one of the sixth pair of impurityregions is electrically connected to the first conductive layer via afourth shared contact.
 10. The semiconductor memory according to claim4, wherein the respective one electrodes in the first to fourthconductive layers are disposed separately.
 11. The semiconductor memoryaccording to claim 4, wherein the first and third conductive layers arearranged in an approximately straight line along the direction offormation of the first word line, and the second and fourth conductivelayers are arranged in an approximately straight line along thedirection of formation of the second word line.